Organized by IEEE-CPMT since 2006, the Electronics System Integration Technology Conference ESTC conference series is the premier venue for academics and industry to present and discuss the latest developments in assembly and interconnection technology and new applications. Over 450 conference delegates from more than 35 countries attend each year. This year’s ESTC broke new ground with a technical workshop comprising solely female panelists. The workshop, entitled “Fan-Out Panel: Is the Industry Ready?” included leading designers in the packaging industry, such Beth Keser from Intel Corporation and Fraunhofer IZM’s Tanja Braun to top managers and decision-makers in the field, such Jan Kellar from Deca Technologies, Jan Vardaman from TechSearch International, Marion Weigand from DuPont.

Organized and moderated by Beth Keser, the workshop emerged into a lively discussion of fan-out technology from many different angles. Questions ranged from why some companies are still reluctant to embrace the technology to the nitty-gritty of implementation, such as technology strategy (Fab-like or PCB-like), suggested panel size, preferred through-via connection technologies and timeline to production.

Strong opinions were exchanged on the SEMI Three-Dimensional Packaging and Integration (3DP&I) Technical Committee’s recent FO-PLP task force to develop a panel standard for size, but also edge profile, warpage, and flatness, by canvasing input via an industry-wide ballot. Overall, the workshop provided a fascinating behind-the-scenes look at the challenges and potential of implementing new technology across a decentralized, but nevertheless horizontally and vertically integrated industry.