Fraunhofer Institute for Reliability and Microintegration IZMCu-TSV Process Line at ASSID/Dresden
800 m² cleanroom (+ 220 m² laboratory)
300 (200) mm wafer process line for wafer level 3D system integration:
- Copper TSV technology
- High density multilayer thin film technology (RDL)
- Wafer thinning and handling technologies (Temporary Bond- / Debonding)
- Wafer level bumping technologies (ECD)
- Wafer level assembly and chip stacking