Trainings and Workshops

Fan-out Wafer and Panel Level Packaging are latest trends in microelectronics and have significantly developed towards a packaging platform for heterogeneous system integration. Fan-out Packaging technologies options range from 2D single and multichip integration to 2,5D solutions for Package-on-Package (PoP) or to embedded bridge approaches for high density routing needs. FO-Packaging also enables the integration of additional packaging options as exposed die, microfluidics integration, antenna in package (AiP) in 2D and 3D and also thermal solutions as package integrated heat spreaders. While FO-WLP is already in volume production at various OSATS, panel level packaging with its large form factors of 300x300, 510x515 or 456x610 mm² is gaining momentum with the advent of chiplet technology and the application to large body size packages e.g. HPC modules. Here a key driver is the potential for cost reduction, that comes with the additional benefit of lowering the CO2 footprint of the final package by increasing process & material efficiency due to the optimized form factor.