Trainings and Workshops

As the miniaturization of semiconductor chips is a major challenge, minimizing the wiring length in the package by using denser and thinner connections is critical. The high number of inputs and outputs (I/O) in these high-density packages reduces the structural size of leads and spaces (L/S), and the quality of interconnection of these fine spaces can drastically affect the performance of the device.

This session will presents the development of the necessary technology blocks for high-density redistribution layers required to realize such organic substrates.

The technology used is advanced semi-additive processing (aSAP) at large panel level size. This technology involves the use of dielectric layers such as ABF or similar, PVD seeding and additive electrolytic copper deposition.

The various interconnect blocks required are discussed in detail:

Vertical interconnects can be made by laser drilling, lithography if photoimageable dielectrics are used, or plasma with reactive ion etching (RIE). The process capabilities and limitations are discussed in detail.

Horizontal interconnects are fabricated by seeding, photo-imaging masks and subsequent copper deposition, and resist and seed removal. Photo-imaging is an important step in this process. The development towards line and space structures targeting 5µm and further 2µm on large panels up to 6510x515mm² is described in detail.

Finally, initial electrical test data and the resulting process yield for various structure sizes are presented and discussed.