Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM
- Test Wafer
- multi project wafer (MPW-USEP001)
- Package Size: 10 mm x 10 mm x 0.7 mm
- Number of IOs: 377 (24x24 partially populated), 0.4 mm pitch, 0.25 mm ball diameter
- SoC/Flip-Chip: functional test die / 2 Memory ICs (100 µm thick) with capillary underfill
- Layer stack: 1 RDL layer on SoC side, 1 interconnect layer (FC-land), 15 µm line/space
Package
- Package size: 10 mm x 10 mm xx 0.22 mm
- Number of IO: 144 (12x12 array), 0.8 pitch, 84 TPVs
- SoC: 5 mm x 5 mm daisy chain test chip (25 individual chains, 1600 FC interconnects)
- Layer stack: 2 layer RDL-1st, 10 µm line/space, 1 layer RDL on top side, 3 interconnect layer
- Sensor on top: pressure, acceleration, temperature, environment (gas)